In the packaging of integrated circuits, particular flip chip packaging, warpage and stress are generated due to the mismatch in Coefficients of Thermal Expansion (CTEs) between different materials and different package components. The warpage and stress are major concerns in the improvement in the reliability of package structures. The current solution for reducing the warpage is to bond stiffener rings on package components such as package substrates. Metal lids are also bonded to the stiffener ring.
Although the stiffener rings can reduce the warpage of the package substrates, the resulting packages will be constrained by the stiffener rings, resulting in higher interfacial stresses for the package components, for example, the solder bumps and the dies. In the reliability tests in which the package structures experience multiple cycles of cooling and heating processes, the stresses may cause bump cracks, which indicate the reliability problems in the package structures.